Arizona Microtek, Inc.
AZT71
Programmable Capacitive Tuning IC
For an example of writing bits into the EEPROM, suppose the desired capacitance is 7.23pF. The control word becomes
‘00000010100’ (Figure 8). Also suppose the EEPROM bits have been erased and therefore logic high (The AZT71 is
initially shipped in this condition). Since bit0 is the first bit to be loaded, the bit sequence becomes 0-0-1-0-1-0-0-0-0-0-0.
However, as described before, selecting bits for the EEPROM are active LOW, which will invert the logical values in the
sequence to 1-1-0-1-0-1-1-1-1-1-1 (Figure 9). Note the differences between the EEPROM bits and the converted control
word. Since there are 2 differences, two write cycles are required as only 1 bit should be written at a time. Figure 10
shows the timing for bit2 while Figure 11 shows the timing for bit4.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
Figure 8 – Desired control word
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
DA
difference
difference
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
EEPROM
Figure 9 – Converted control word and differences from known EEPROM states
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
DA
CLK
PV
bit 0
loaded 1st
bit 10
loaded last
10ms
min
≥5.6V,
≤6.1V
4µs
min
t
Figure 10 – First programming cycle to program bit2 into the EEPROM
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+1-480-962-5881
7
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May 2012, Rev 1.2
AZM [ ARIZONA MICROTEK, INC ]
