ARIZONA MICROTEK, INC.
AZ10E131
AZ100E131
ECL/PECL 4-bit D Flip-Flop
FEATURES
PACKAGE AVAILABILITY
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1100 MHz Min. Toggle Frequency
PACKAGE
PART NUMBER
MARKING
NOTES
Differential Outputs
AZM10E131
Individual and Common Clocks
PLCC 28
AZ10E131FN
1,2
<Date Code>
Individual Resets (asynchronous)
AZM100E131
PLCC 28
AZ100E131FN
1,2
Paired Sets (asynchronous)
<Date Code>
Operating Range of 4.2V to 5.46V
1
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
75kΩ Internal Input Pulldown Resistors
2 Date code format: “YY” for year followed by “WW” for week.
Direct Replacement for On Semiconductor
MC10E131 & MC100E131
DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be
clocked separately by holding Common Clock (C
C
) LOW and using the Clock Enable (CEn) inputs for clocking.
¯¯
Common clocking is achieved by holding the CEn inputs LOW and using C
C
to clock all four flip-flops. In this
¯¯
case, the CEn inputs perform the function of controlling the common clock to each flip-flop.
¯¯
Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs,
with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both C
C
and CEn are LOW, and transfers to the slave when either C
C
or CEn (or
¯¯
¯¯
both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
R3
D2
CE2
R2
V
CCO
21
Q3
Q3
CE3
25
26
24
23
22
20
19
18
Q2
D3
27
17
Q2
S12
28
16
V
CC
Q1
V
EE
1
Pinout: 28-Lead
PLCC (top view)
15
C
C
2
14
Q1
S03
3
13
Q0
D0
4
12
Q0
5
6
7
8
9
10
11
CE0
R0
D1
CE1
R1
NC
V
CCO
* All V
CC
and V
CCO
pins are tied together on the die.
1630 S. STAPLEY DR., SUITE 127
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MESA, ARIZONA 85204
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USA
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(480) 962-5881
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FAX (480) 890-2541
www.azmicrotek.com
AZM [ ARIZONA MICROTEK, INC ]
