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AS4SD16M72PBG-75/XT 参数 Datasheet PDF下载

AS4SD16M72PBG-75/XT图片预览
型号: AS4SD16M72PBG-75/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 16M X 72 , SDR SDRAM MCP [16M x 72, SDR SDRAM MCP]
分类和应用: 内存集成电路动态存储器
文件页数/大小: 16 页 / 199 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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AS4SD16M72PBG-s/IT,ET,XT  
16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO  
Pin Descriptions  
BGA Locations  
F4, F16,  
L2, L13,  
SYMBOL  
CKx  
DESCRIPTION  
Clock: CKx is the clock input. All address and  
control input signals are sampled on the crossing of the positive  
edge of CKx\. Output data (DQ's and  
DQS) is referenced to rising edge of CLKx  
Clock Enable: CKE controls the clock inputs. CKE high enables,  
CKE Low disables the clock input pins. Driving CKE Low pro-  
vides PRECHARGE POWER-DOWN and SELF REFRESH  
operations, or ACTIVE POWER-DOWN. CKE is synchronous  
for POWER-DOWN entry and exit, and for SELF REFRESH entry  
CKE is Asynchronous for SELF REFRESH exit and for disabling  
the outputs. CKE must be maintained HIGH throughout read and  
write accesses. Input buffers are disabled during POWER-DOWN  
Input buffers are disabled during SELF REFRESH.  
G4, G16, K2, K13  
M6  
CKEx  
Chip Select: CSx\ enagles the COMMAND register(s) of each of  
the five (5) contained words. All commands are masked when CSx\  
is registered HIGH. CSx\ provides for external bank selection  
on systems with multiple banks. CSx\ is considered part of the  
COMMAND CODE.  
G1, G13, K4, K16  
M12  
CSx\  
Command Inputs: RASx, CASx, and Wex\ define the command  
being entered  
F4, F16, G5, G15,  
K1, K12, L2, L13,  
N7, M9  
RASx\, CASx\  
WEx\  
Input Data Mask. DM is an input mask signal for write data.  
Input data is masked when DQMLx or Hx is sampled HIGH at  
time of a WRITE access. DM is sampled on both edges of DQSLx  
and DQSHx  
G4, G16, K2, K14  
M7  
DQMLx, DQMHx  
Bank Address Inputs: BA0, BA1 define which bank an ACTIVE  
READ, WRITE, or PRECHARGE command is being applied  
Address Input: Provide the row address for Active commands, and  
the column address and auto precharge bit (A10) for READ/WRITE  
commands to select one location out of the memory array int the  
respective bank. A10 sampled during a PRECHARGE command  
determines whether the PRECHARGE applies to one bank or  
all banks. The address inputs also provide the op-code during  
a MODE RESIST ER SET command.  
E8, E9  
BA0, BA1  
A7, A8, A9, A10, B7 A0-A11, A12  
B8, B9, B10, C7, C8  
C9, C10, D7  
Austin Semiconductor, Inc.  
Proprietary Material  
ASI Product Marketing