iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR232M64PBG
Description
BGA Locations
Symbol
ODT
Type
L6
CNTL Input On-Die-Termination: Registered High enables on data bus termination
CNTL Input Differential input clocks, one set for each x16bits
F4, F16, G5, G15, K12
L13, L2, K1
CKx, CKx\
G4, G16, K13, K2
CKEx
CNTL Input Clock enable which activates all on silicon clocking circuitry
G1, G13, K16, K4
F12, G2, K15, L5
F1, G12, L16, L4
F2, F13, L15, M4
E4, F15, M13, M2
E2, E13, M15, M5
E5, E7, E11, N12
F6, F8, F10, L11
CSx\
RASx\
CASx\
Wex\
CNTL Input Chip Selects, one for each 16 bits of the data bus width
CNTL Input Command input which along with CAS\, WE\ and CS\ define operations
CNTL Input Command input which along with RAS\, WE\ and CS\ define operations
CNTL Input Command input which along with RAS\, CAS\ and CS\ define operations
CNTL Input One Data Mask cntl. for each upper 8 bits of a x16 word
UDMx
LDMx
UDQSx
UDQSx\
CNTL Input One Data Mask cntl. For each lower 8 bits of a x16 word
CNTL Input Data Strobe input for upper byte of each x16 word
CNTL Input Differential input of UDQSx, only used when Differential DQS mode is enabled
E6, E10, F5, L12
F7, F11, G6, L10
LDQSx
LDQSx\
CNTL Input Data Strobe input for lower byte of each x16 word
CNTL Input Differential input of LDQSx, only used when Differential DQS mode is enabled
A7, A8, A9, A10, B7,
B8, B9, B10, C7, C8,
C9, C10, D7
Ax
Input
Array Address inputs providing ROW addresses for Active commands, and
the column address and auto precharge bit (A10) for READ/WRITE commands
D8, D9, D10
DNU
BA0, BA1
DQx
Future Input
Input
E8, E9
Bank Address inputs
A2, A3, A4, A13, A14,
A15, B1, B2, B3, B4,
B13, B14, B15, B16,
C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2,
D3, D4, D13, D14, D15,
D16, E1, E16, M1, M16,
N1, N2, N3, N4, N13, N14
N15, N16, PP1, P2, P3,
P4, P13, P14, P15, P16,
R1, R2, R3, R4, R13, R14
R15, R16, T2, T3, T4, T13
T14, T15
Input/Output Data bidirectional input/Output pins
E12
Vref
VCC
Supply
Supply
SSTL_18 Voltage Reference
Core Power Supply
B11, B12, C5, C6,E3,
F3, G3, H3, H12, H16,
J3, J12, J16, K3, L3,
M3, P11, P12, R5, R6,
T16
A11, A12, D5, D6, H4,
H15, J4, J15, T5, T6
A5, A6, A16, B5, B6,
C11, C12, D11, D12,
E14, F14, G14, H1, H2,
H14, J1, J2, J5, J13,
J14, K14, L14, M14, P5,
P6, R11, R12, T1, T11,
T12
VCCQ
VSS
Supply
Supply
I/O Power
Core Ground return
G7, G8, G9, G10, H7,
H8, H9, H10, J7, J8, J9,
J10, K7, K8, K9, K10
E15, F9, G11, H6, H11, J6,
J11, K11, L1, L8, L9, N7,
N8, N9, N10, P7, P8, P9,
P10, R7, R8, R9, R10, T7,
T8, T9, T10, K5, K6, L7,
M6, M7, M8, M9, M10,
M11, M12, N5, N6, N11
VSSQ
NC
Supply
I/O Ground return
No connection
A1
UNPOPULATED
Unpopulated ball matrix location (location registration aid)
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR232M64PBG
Rev. 1.3 6/09
3
AUSTIN [ AUSTIN SEMICONDUCTOR ]
