Low voltage, Low power, ±1% High detect accuracy with delay circuit CMOS Voltage Detector
Rev. E13-01
VDD Series
DESCRIPTION OF OPERATION
ò
General operation (CMOS Output)
In reference to following the block diagram of CMOS output VDD series ;
V
IN
+
_
Delay
Circuit
P-ch
N-ch
Voltage
Reference
V
OUT
Vss
A. When the input voltage (VIN) is higher than the release voltage (VREL), the input voltage (VIN) is
provided at the output terminal because N-ch transistor is OFF and the P-ch transistor is ON. And,
the output maintains the same level of input as long as the input voltage remains above the detection
voltage (VDET).
B. When the input voltage (VIN) falls below the
detection voltage (VDET), the N-ch transistor
is ON and the P-ch transistor is OFF. And,
the output voltage (VOUT) is same as ground
level (VSS).
[ TIMING CHART ]
Input voltage (VIN
)
Release voltage (VREL
)
C. When the input voltage (VIN) falls below the
min. operating voltage, the output becomes
unstable, or goes to VIN when the output is
Detection voltage (VDET
)
pulled up to VIN
.
Min. operating voltage
Power ground (VSS
)
D. When the input voltage (VIN) rises above the
minimum voltage, the ground voltage (VSS
)
level is maintained even though the input
voltage (VIN) rises above the detection
voltage (VDET) as long as it does not exceed
the release voltage (VREL) level.
Output voltage (VOUT
)
Release voltage (VREL
)
Detection voltage (VDET
)
)
E. Following delay time, the N-ch transistor
Hysteresis range (VHYS
becomes OFF when the input voltage (VIN
)
Delay time (TDLY
Min. operating voltage
Power ground (VSS
)
rises above the release voltage (VREL), and
the P-Ch transistor becomes ON. And, the
output voltage (VOUT) is equal to input
voltage (VIN). This difference between VDET
and VREL is hysteresis range (VHYS).
)
A B
C
D E
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