2.488 GBPS – 2.7 GBPS QUAD MUX WITH FAN OUT BUFFERS
S3053
Table 2. Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin#
Description
Int.
Biased
Diff.
42
41
50
51
INA0P
INA0N
INA1P
INA1N
Differential inputs to the multiplexer.
I
LVPECL
Int.
Biased
Diff.
29
28
37
38
IND0P
IND0N
IND1P
IND1N
Differential inputs to the multiplexer.
I
I
LVPECL
SELA
SELD
A Low selects IN0. When High, this signal selects IN1.
Serial output from Mux B.
43
36
LVTTL
17
18
23
22
OUTB0P
OUTB0N
OUTB1P
OUTB1N
Diff.
CML
O
4
5
10
9
OUTC0P
OUTC0N
OUTC1P
OUTC1N
Serial output from Mux C.
Diff.
CML
O
I
SELB
SELC
A Low selects Mux A output. When High, this signal selects the
Mux D output.
49
30
LVTTL
6, 8, 19,
20, 21,
32, 34,
45, 46,
47,
VCC
Power Supply. 3.3V nominal.
15
25
2
VSWB0
VSWB1
VSWC0
VSWC1
Voltage Swing Control pin.
Ground.
Analog
I
12
1, 7, 13,
14, 26,
27, 31,
33, 35,
39, 40,
44, 48,
52,
VEE
16
24
3
VEEB0
VEEB1
VEEC0
VEEC1
Ground for B0, B1, C0, C1.
Output
GND
11
4
October 10, 2000 / Revision D
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
