Part Number S3033
Revision 1.0 - January 20, 2000
S3033
Board Decoupling Guidelines
SONET/SDH/ATM OC-3/12 Transceiver S3033 Example
APPLICATION NOTE
The S3033 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 (622.08 Mbit/s) and
OC-3 (155.52 Mbit/s) interface device. Figure 1 illustrates the connections for the S3033 device. External capaci-
tors are required for power supply decoupling only. The inductor is a Murrata BLM31B601SPB or BLM11B601SPB
surface mount ferrite. The double capacitors shown are parallel 0.1
µ
F X7R and 100 pF are COG or NPO ceramic
chip. The CAP1/CAP2 capacitor should be 0.01
µ
F X7R. Note that the 0.1
µ
F should be placed on the bottom side
of the board for better capacitor efficiency. The Low ESR 10
µ
F capacitor and 0
Ω
resistor are optional for AVCC,
for higher noise environments.
Figure 1. S3033 Connections
TTLINGND
TTLINVCC
0.1
µ
F
64
63
62
61
60
59
0.1
µ
F
1 TXCOREGND
2 TXCOREVCC
3
4
5
6
7
58
57
56
55
54
53
52
51
50
49
48
TTLVCC 47
46
45
44
43
42
41
40
TTLVCC 39
38
0.1
µ
F
0.1
µ
F
+3.3 Volt VCC Plane
+3.3 Volt VCC Plane
(Optional)
L
0
10
µ
F
(Optional)
0.1
µ
F
0.1
µ
F
100 pF
31 RXCOREGND
32
100 pF
AVCC1
AGND1
8 CAP2
9 CAP1
10 AGND0
11 AVCC0
S3033
Pinout
Top View
64 Pin PQFP
23
24
25
26 RSCLKGND
27 RSCLKVCC
TTLGND
18
19 TXOUTGND
12
13
14
TXOUTVCC
0.1
µ
F
100 pF
28
29
30 RXCOREVCC
37
36
35
34
33
TTLGND
17
20
21
22
15
16
100 pF
0.1
µ
F
0.1
µ
F
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
