®
DEVICE
SPECIFICATION
SERIAL BACKPLANE RETIMER DEVICE
BiCMOS PECL CLOCK GENERATOR
SERIAL BACKPLANE RETIMER DEVICE
GENERAL DESCRIPTION
S2092
S2092
FEATURES
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•
•
On-chip high frequency PLL with internal
loop filter for clock recovery
Internal 100
Ω
line-to-line termination on
high speed differential input
Supports data recovery from:
2.488 to 2.67 Gbps (2.488 Gbps with FEC
overhead data rate capability)
Selectable reference frequencies
Lock detect—monitors frequency of
incoming data
Low-jitter serial CML interface
Single +3.3 V supply, 455 mW power
dissipation (typ)
Compact 7 mm x 7 mm 48 pin TQFP/TEP
package
The function of the S2092 retimer device is to derive
high speed timing signals for DWDM equipment. The
S2092 is implemented using AMCC’s proven Phase
Lock Loop (PLL) technology. Figure 1 shows a typical
network application.
The S2092 can receive a 2.488 Gbps to 2.67 Gbps
scrambled NRZ signal. This range is dependent on
the user's FEC needs and reference frequency selec-
tion. The S2092 recovers the clock from the data
and outputs the retimed data.
The S2092 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
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•
•
•
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APPLICATIONS
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•
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Dense Wavelength Division Multiplexing
(DWDM) systems
Serial Backplane interfaces
2.488 Gbps to 2.67 Gbps Short Haul
Retiming
Crosspoint interfaces
Figure 1. System Block Diagram
Port Card
S3056
S3057
S3052
S3056
S3056
S3057
S3052
S3057
S2092
S2092
S3057
Port Card
S3057
S3052
Switch Card
S2092
S2092
S3056
S3057
S3052
S2018
S2092
S3056
S3057
S3052
S3056
S3056
S3057
S3052
S3057
S3057
S3052
S3057
S2092
S2092
S2092
S3056
S3057
S3052
Port Card
Port Card
July 10, 2000 / Revision A
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
