Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
PPC440GX Functional Block Diagram
Data Sheet
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
63 internal
18 external
UART
IIC
PPC440
Processor Core
GP
Timers
GPIO
x2
x2
DCR Bus
Trace
JTAG
On-chip Peripheral Bus (OPB)
Arb
32KB
32KB
D-Cache
I-Cache
DMA
Controller
(4-Channel)
OPB
Bridge
SRAM
256KB
L2 Controller
Processor Local Bus (PLB)
External
Bus
External
TAH
Bus Master
10/100
x2
MAL
Controller Controller
10/100/
1000 x2
83MHz max
32-bit addr
32-bit data
Ethernet
I2O
Messaging
PCI-X
Bridge
DDR SDRAM
Controller
ZMII
RGMII
Bridge
Bridge
1 GMII
or
2 RGMII
or
1 MII
or
2 RMII
or
133MHz max 166MHz max
13-bit addr
32/64-bit data
32/64-bit data
1 TBI
or
4 SMII
2 RTBI
The PPC440GX is designed using the IBM® Microelectronics Blue Logic™ methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus™ Architecture.
Note: IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 200MHz
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GX processor through the use of mtdcr and mfdcr instructions.
6
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
