Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Block Diagram
Figure 2. PPC440GRx Functional Block Diagram
10
Clock
Control,
Reset
External
Power
Mgmt
Interrupts
66MHz max
- 32 bits
- 6 devices
83MHz max
- 30-bit addr
- 32/16-bit data
DCRs
Timers
MMU
UIC
PPC440
DCR Bus
Processor
External
Peripheral
Controller
NAND
PCI
Trace
JTAG
Flash
Bridge
Controller
32KB
32KB
D-Cache
I-Cache
Security
(optional)
SRAM
16KB
PLB
Bridge
(X-bar)
PLB (PLB4—128 bits)
PLB (PLB3—64 bits)
DMA
DMA
Controller
OPB
Bridge
GPT
BSC
Controller
DDR2/1
SDRAM
Controller
On-chip Peripheral Bus (OPB 0)
Ethernet
10/100/1000
x2
IIC
UART
x4
SPI
GPIO
333MHz max
x2
MAL
data rate
- 14-bit addr
- 64/32-bit data
RGMII
ZMII
™
The PPC440GRx is a system on a chip (SOC) using IBM CoreConnect Bus Architecture.
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
