nP3710
– Context Memory:
High Performance nPcore
Three nPcores at up to 700 MHz
Integrated Coprocessors
nP3710 Highlights
Interfaces
Two banks of 36-bit RLDRAM II
operating at up to 250 MHz (32 Gbps
with ECC)
•
•
Line Interfaces – cell and packet
•
Policy Engine for efficient packet
classification
– Channel Service Memory:
One bank of 36-bit QDR-II SRAM
operating at up to 250 MHz
SPI-3/UT-3
1
GE
4
SPI-4.2
1
•
Special Purpose Unit (SPU) for per-flow
policing
nP3710
– Flow Database Memory:
Two banks of 18-bit QDR-II SRAM
operating at up to 250 MHz
•
•
Hashing Unit
•
•
Support for Deep Channelization: for
OC-1s, T3/E3s, T1/E1s, etc.
On-Chip Debugger (OCD)
Integrated Traffic Manager
•
Fabric Interface: OIF SPI-4 Phase 2
– 800 MHz
•
•
CPU Interfaces: PowerPC and Gigabit
Ethernet
Hierarchical Traffic Manager with
fine-grained flow-based traffic
management
•
External Memory Interfaces:
RLDRAM II memory controllers
External Search Interface
– Compliant with NPF
•
Leverages field-proven nPX5710 and
nPX5720 technology
– Payload Memory:
– Backward compatibility mode with
existing TCAMs
Two banks of 36-bit RLDRAM II
operating at up to 250 MHz (32 Gbps
with ECC)
•
•
Debug port
JTAG port
18
36
36
36
36
36
36
NPF(QDR)
QDR
RDLRDARMAM
DRRALMD/SRRAAMM
SPI3/UT3
QAB
Scratch
Pad
Hash
Policy
Engine
XMI
XSC
SPU
Engine
Cache
Memory Access Unit
GE
GE
GE
GE
3 nPcores @ 700 MHz
nPcore @ 700 MHz
Soft TM
24 Tasks
72 Tasks
Traffic
Manager
FE/GE
MACs
SPI4.2
Statistics
Engine
Queuing
Scheduling
Line
Interfaces
(CSM)
Packet Transform
Packet Transform
Engine
Engine
(PTE)
(PTE)
HOHSOT SCTPUCPU
16-bit
DEBUG
DEBUG
FCN
JTAG
nP3710 Block Diagram
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
