Revision 2.04 – September 7, 2007
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
PPC405GPr Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
OCM
SRAM
Power
Mgmt
DCRs
Timers
MMU
DOCM
IOCM
OCM
Control
PPC405
Processor Core
GPIO
IIC
UART
UART
DCR Bus
Trace
ICU
JTAG
DCU
16KB
I-Cache
16KB
D-Cache
On-chip Peripheral Bus (OPB)
OPB
Arb
DMA
Controller
MAL
Ethernet
Bridge
(4-Channel)
Arb
Processor Local Bus (PLB)
Code
Decompression
(CodePack™)
External
Bus
Controller
External
SDRAM
Controller
Bus Master
PCI Bridge
Controller
66 MHz max (async)
33 MHz max (sync)
MII
13-bit addr
32-bit data
32-bit addr
32-bit data
®
TM
The PPC405GPr is designed using the IBM Microelectronics Blue Logic methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
TM
way to create complex ASICs using IBM CoreConnect Bus Architecture.
6
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
