Preliminary
January 2006
included to ensure high noise immunity and prevent
false tripping.
5. The maximum difference of PVIN between
any 2 devices should be less than 50mV.
Parallel Device Operation
VSENSE
VIN
VOUT
CIN-1
EN5365
(MASTER) POK
VS0
VS1
VS2
COUT-1
In order to power a load that is higher than the rated
6A of the EN5365, from 2 to 4 devices can be placed
in parallel for providing a single load with up to 24A
of output current.
PWM ENABLE M/S
VIN
VOUT
POK
VS0
AGND
VS1
VS2
ENABLE
PWM ENABLE
VIN
VOUT
Paralleling more than 1 device is accomplished by
selecting a master device and tying that M/S pin to
AGND. All slave devices should have their M/S pin
tied to AVIN. The PWM pin from the master device is
connected to all slave device PWM pins. (See
schematic below)
CIN-2
EN5365
(SLAVE)
VS0
VS1
VS2
COUT-2
M/S
AVIN
Figure 4 . Paralleling of two devices.
Compensation
1. All master and slave devices should have
identical placement and values of input, output
and soft-start capacitors.
The EN5365 is internally compensated through the
use of a type 3 compensation network and is
optimized for use with about 50µF of output
capacitance and will provide excellent loop bandwidth
and transient performance for most applications. (See
the section on Capacitor Selection for details on
recommended capacitor types.) Voltage mode
operation provides high noise immunity at light load.
2. All master and slave devices should have their
ENABLE pins tied together and should be
operated simultaneously.
3. The master and slave voltage select pins, VS0,
VS1, and VS2, must be set to the same
settings. It is recommended that the slave pins
be connected to the master voltage select pins
to avoid accidental code difference.
4. The maximum board trace resistance between
any 2 devices VOUT pins should be less than
10mΩ.
In some cases modifications to the compensation may
be required. For more information, contact Enpirion
Applications Engineering support.
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom Of Package
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall
foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package.
Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC
board. PWB solder mask must be used to prevent connection to the other pads. Figure ZZ shows the shape and
location of these metal pads as well as the mechanical dimension of the large thermal pad and the pins. The
“grayed-out” area represents the area that should be protected by solder mask on the PWB.
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