Stratix II EP2S60 DSP Development Board Data Sheet
Table 1 describes the components on the board and the interfaces it
supports.
Table 1. Stratix II EP2S60 DSP Development Board Components & Interfaces (Part 1 of 2)
Component/
Interface
Board
Designation
Type
Description
Components
Stratix II device
MAX Device
FPGA
U18
EP2S60 Stratix II device
PLD
I/O
U10
EPM7256ETC144 device
A/D converters
D/A converters
1 MByte SRAM
U1, U2
U14, U15
U43, U44
Two 12-bit 125-MHz A/D converters
Two 14-bit 165-MHz D/A converters
I/O
Memory
1 MByte of 10-ns asynchronous SRAM configured as a
32-bit bus.
16 MBytes of flash
memory
Memory
Memory
Input
U17
16 Mbytes of flash memory configured as an 8-bit bus.
32 MBytes of
SDRAM
U39, U40
J10, J11, J12
U12, U13
32 MBytes of SDRAM memory configured as a 64-bit
bus
SMA external clock
input connectors
SMA connectors for inputs of external clock signals,
terminated in 50 Ω.
Dual seven-segment Display
display
Dual seven-segment display.
Push-button
switches
I/O
SW4, SW5,
SW6, SW7
Four push-button switches, which are user-defined as
logic inputs.
User-defined LEDs
Power-on LED
Display
Display
D1 - D8
LED7
Eight user-defined LEDs.
LED that illuminates when power is supplied to the
board.
CONF_DONE LED
RS-232 connector
Display
I/O
LED5
J29
LED that illuminates upon successful configuration of
the Stratix II device.
DB9 connector, configured as a DTE serial port. The
interface voltages are converted to 3.3-V signals and
brought to the Stratix II device, which must be
configured to generate and accept transmissions.
100-MHz oscillator
Clock
Input
Y1
Socketed on-board 100-MHz oscillator.
Single 16-V DC
power supply
J22 (adapter)
Board adapter for included 16-V DC power supply
Stratix II device Joint I/O
Test Action Group
(JTAG) Connector
J21
J13
JTAG Connector used to configure the Stratix II device
directly
Configuration
controller JTAG
Connector
I/O
JTAG connector used to configure the configuration
controller
4
Altera Corporation
Preliminary
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