Cyclone V Device Overview
CV-51001 | 2018.05.07
Resource
Member Code
C3
52
52
1
C4
84
84
2
C5
84
84
2
C7
120
120
2
C9
140
140
2
LVDS
Transmitter
Receiver
PCIe Hard IP Block
Hard Memory Controller
1
2
2
2
2
Related Information
True LVDS Buffers in Devices, I/O Features in Cyclone V Devices
Provides the number of LVDS channels in each device package.
Package Plan
Table 7.
Package Plan for Cyclone V GX Devices
Member
M301
M383
M484
U324
U484
Code
(11 mm)
(13 mm)
(15 mm)
(15 mm)
(19 mm)
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
—
GPIO
XCVR
3
GPIO
XCVR
C3
C4
C5
C7
C9
—
129
129
—
—
4
—
175
175
—
—
6
—
—
144
—
208
224
224
240
240
3
6
6
6
5
—
—
4
6
—
—
—
—
—
—
—
—
240
—
3
—
—
—
—
—
—
—
Member
Code
F484
F672
(27 mm)
F896
(31 mm)
F1152
(35 mm)
(23 mm)
GPIO
XCVR
GPIO
—
XCVR
GPIO
XCVR
—
GPIO
—
XCVR
—
C3
C4
C5
C7
C9
208
240
240
240
224
3
6
6
6
6
—
6
—
—
336
336
336
336
—
—
—
6
—
—
—
—
9
480
480
9
—
—
9
12
560
12
Cyclone V GT
This section provides the available options, maximum resource counts, and package
plan for the Cyclone V GT devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Product Selector Guide.
Related Information
Product Selector Guide
Provides the latest information about Intel products.
Cyclone V Device Overview
9
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