AV-51001
2013.05.06
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Maximum Resources
Maximum Resources
Table 6: Maximum Resource Counts for Arria V GT Devices—Preliminary
Member Code
Resource
C3
156
58,900
235,600
10,510
961
396
792
10
C7
242
D3
362
D7
Logic Elements (LE) (K)
504
ALM
91,680
366,720
13,660
1,448
800
136,880
547,520
17,260
2,098
1,045
2,090
12
190,240
760,960
24,140
2,906
1,156
2,312
16
Register
M10K
MLAB
Memory (Kb)
Variable-precision DSP Block
18 x 18 Multiplier
PLL5
1,600
12
6 Gbps6
10 Gbps7
3 (9)
4
6 (24)
12
6 (24)
12
6 (36)
20
Transceiver
GPIO8
416
68
544
704
704
Transmitter
120
160
160
LVDS
Receiver
80
136
176
176
PCIe Hard IP Block
1
2
2
2
Hard Memory Controller
2
4
4
4
Related Information
High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook
Provides the number of LVDS channels in each device package.
Transceiver Architecture in Arria V Devices
Describes 10 Gbps channels usage conditions.
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The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs.
The 6 Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10 Gbps
channels as three 6 Gbps channels-the total number of 6 Gbps channels are shown in brackets.
Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture
in Arria V Devices chapter. For information about 10 Gbps SFF-8431 compliance, contact Altera.
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os
includes transceiver I/Os.
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Arria V Device Overview
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