AS7C1024B
®
Write waveform 2 (CE1 and CE2 controlled)10,11,12
t
WC
t
t
AH
AW
t
WR
Address
t
t
, t
AS
CW1 CW2
CE1
CE2
t
WP
WE
tWZ
t
t
DW
DH
D
Data valid
IN
D
OUT
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.5V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
+5V
Thevenin equivalent:
168
+1.728V
480
Ω
Ω
D
OUT
D
+3.5V
GND
OUT
13
90%
10%
90%
10%
255
Ω
C
2 ns
Figure A: Input pulse
GND
Figure B: 5V Output load
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE1 and OE are low and CE2 is high for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
3/26/04, v 1.2
Alliance Semiconductor
P. 6 of 9