AS4C16M16SA
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
NOP
READ A
NOP
NOP
WRITE B
DIN B0
NOP
NOP
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DIN B1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
Don’t Care
Figure 7. Read to Write Interval
(Burst Length 4, CAS# Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
DIN B0
NOP
NOP
COMMAND
CAS# Latency=3
tCK3, DQ
DOUT A0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
Don’t Care
≧
Figure 8. Read to Write Interval
(Burst Length
4, CAS# Latency = 3)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank. The following figure shows the optimum time that BankPrecharge/
PrechargeAll command is issued in different CAS latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank
Row
Bank (s)
ADDRESS
tRP
READ A
NOP
NOP
NOP
Precharge
NOP
NOP
Activate
NOP
COMMAND
CAS# Latency=2
tCK2, DQ
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
CAS# Latency=3
tCK3, DQ
DOUT A3
Figure 9. Read to Precharge
(CAS# Latency = 2, 3)
Confidential
9
Rev. 2.0 63nm Mar /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
