A24C02
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
2k BITS (256 X 8) TWO-WIRE SERIAL
FUNCTIONAL DESCRIPTION
1. Memory Organization
A24C02, 2k SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2k requires an 8- bit
data word address for random word addressing.
2. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (see Figure 1 on page 10). Data changes during SCL
high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede
any other command (see Figure 2 on page 10).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence,
the stop command will place the EEPROM in a standby power mode (see Figure 2 on page 10).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the
ninth clock cycle.
STANDBY MODE: The A24C02 features a low-power standby mode which is enabled: (a) upon power-up
and (b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be
reset by following these steps:
1.
2.
3.
Clock up to 9 cycles.
Look for SDA high in each cycle while SCL is high.
Create a start condition.
REV2.1
- SEP 2008 RELEASED, JUN 2017 UPDATED -
- 7 -
AITSEMI [ AiT Semiconductor ]
