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AT1362B 参数 Datasheet PDF下载

AT1362B图片预览
型号: AT1362B
PDF下载: 下载PDF文件 查看货源
内容描述: 同步降压转换器具有电源状态良好探测器及LDO [Synchronous Buck Converter With Power Good Detector & LDO]
分类和应用: 转换器
文件页数/大小: 13 页 / 700 K
品牌: AIMTRON [ AIMTRON TECHNOLOGY ]
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AT1362A/B  
Preliminary Product Information  
Synchronous Buck Converter  
With Power Good Detector & LDO  
LDO  
For general purposes, use a 2.2uF capacitor on the LDO output. Larger capacitor  
values and lower ESR provide better supply noise rejection and transient response. A  
higher value input capacitor may be necessary if large, fast transients are anticipated .  
Ceramic capacitors have the lowest ESR, and will offer the best AC performance.  
When choosing the input and output ceramic capacitors, choose the X5R or X7R  
dielectric formulations. These dielectrics have the best temperature and voltage  
characteristics of all the ceramics for a given value and size.  
Inductor Selection  
The inductor is chosen based on the desired ripple current. Large value inductors  
lower ripple current and small value inductors result in higher ripple current. Always  
consider the losses associated with the DCR and its effect on the total converter  
efficiency when selecting an inductor. The inductor is selected to limit the ripple  
current to some predetermined value, typically 20~40% of the full load current at the  
maximum input voltage. The formula of inductance value is as below:  
IL = 0.2 ~ 0.4× IOUT (MAX )  
VOUT  
f ×IL  
VOUT  
VIN  
L =  
1−  
IL  
2
(VIN VOUT )×tON  
2× L  
IPK = IO +  
= IO +  
Power Good Indicator with Adjustable Time Delay  
When OUT1 pin is above 2.25V or 1.62V (typ.) and with a delay time (t1) the OUT2  
is start to regulation. The PG pin terminal is an open drain output of N-MOS. Connect  
a resistor from PG pin to VCC or OUT2 to create a logic signal. If OUT2 pin is less  
than 2.97V (typ.) this pin is pulled to ground. When OUT2 pin is above 2.97V (typ.)  
and with a delay time (t2) this pin is open. PG pin is forced low when in UVLO. The  
formula of adjustable delay time is as below:  
0.7V  
IDELAY  
delay time = t1 = t2 = C ×  
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C.  
Tel: 886-3-563-0878  
5/30/2006  
Fax: 886-3-563-0879  
WWW: http://www.aimtron.com.tw  
Email: service@aimtron.com.tw  
REV:1.0  
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