Agilent 16910A and 16911A Specifications and Characteristics
State (Synchronous) Analysis Mode
tWidth* [1]
tSetup
tHold
tSample range [2]
tSample adjustment resolution
Maximum state data rate on each channel
Maximum channels on a single time base
and trigger [4]
Memory depth [4]
(Option 256 is included in base price)
Option 250
1.5 ns
0.5 tWidth
0.5 tWidth
–3.2 ns to +3.2 ns
80 ps typical
250 Mb/s
16910A: 510 – (number of clocks)
16911A: 340 – (number of clocks)
Option 256:
Option 001:
Option 004:
Option 016:
Option 032:
2
4
4
4.0 ns
256 K samples
1 M samples
4 M samples
16 M samples
32 M samples
Option 500
1.5 ns
0.5 tWidth
0.5 tWidth
–3.2 ns to +3.2 ns
80 ps typical
500 Mb/s
16910A: 510 – (number of clocks)
16911A: 340 – (number of clocks)
Option 256:
Option 001:
Option 004:
Option 016:
Option 032:
1
1
N/A
2.0 ns
256 K samples
1 M samples
4 M samples
16 M samples
32 M samples
Number of independent analyzers [5]
Number of clocks [6]
Number of clock qualifiers [6]
Minimum time between active
clock edges* [7]
Minimum master to slave clock time
Minimum slave to master clock time
Minimum slave to slave clock time
*
[1]
[2]
1 ns
1 ns
4.0 ns
N/A
N/A
N/A
[3]
[4]
[5]
[6]
[7]
Items marked with an asterisk (*) are specifications. All others are characteristics.
“Typical” represents the average or median value of the parameter based on measurements from a significant number of units.
Minimum eye width in system under test.
Sample positions are independently adjustable for each data channel input. A negative sample position causes the input to be synchronously sampled by that amount before
each active clock edge. A positive sample position causes the input to be synchronously sampled by that amount after each active clock edge. A sampling position of zero
causes the input to be synchronously sampled coincident with each clock edge.
Use of eye finder is recommended in 450 MHz and 500 Mb/s state mode.
In 250 Mb/s state mode, with all pods assigned, memory depth is half the maximum memory depth. With one pod pair (34 channels) unassigned, the memory depth is full. One
pod pair (34 channels) must remain unassigned for time tags in 500 Mb/s state mode.
Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.
In the 250 Mb/s state mode, the total number of clocks and qualifiers is 4. All clock and qualifier inputs must be on the master modules.
Tested with input signal Vh = +1.3 V, Vl = +0.7 V, threshold = +1.0 V, tr/tf = 180 ps ± 30 ps (10%, 90%).
tWidth
Individual
Data Channel
vHeight
Data Eye
tSetup tHold
Sampling Position
vThreshold
OV
tSample
Clock Channel
8
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