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CA16B2CAA 参数 Datasheet PDF下载

CA16B2CAA图片预览
型号: CA16B2CAA
PDF下载: 下载PDF文件 查看货源
内容描述: CA16型2.5 Gb / s的DWDM转发器,具有16通道155 Mb / s的复用器/解复用器 [CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer]
分类和应用: 解复用器电信集成电路异步传输模式ATM
文件页数/大小: 30 页 / 442 K
品牌: AGERE [ AGERE SYSTEMS ]
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CA16-Type 2.5 Gbits/sDWDMTransponder with  
16-Channel 155 Mbits/s Multiplexer/Demultiplexer  
Advance Data Sheet  
March 2001  
Pin Descriptions (continued)  
Table 1. CA16-Type Transponder Pinout (continued)  
Pin #  
Pin Name  
I/O  
Logic  
Description  
Transmitter Digital Ground  
83  
84  
TxDGND  
TxREFCLKP  
TxREFCLKN  
TxD14P  
TxD14N  
TxDGND  
TxD12P  
TxD12N  
TxD10P  
TxD10N  
TxDGND  
TxD08P  
TxD08N  
TxD06P  
TxD06N  
TxDGND  
TxD04P  
TxD04N  
TxD02P  
TxD02N  
TxDGND  
TxD00P  
TxD00N  
TxDGND  
PCLKP  
I
I
Supply  
LVPECL Transmitter 155 Mbits/s Reference Clock Input  
LVPECL Transmitter 155 Mbits/s Reference ClockInput  
LVPECL Transmitter 155 Mbits/s Data Input  
85  
I
86  
I
87  
I
LVPECL Transmitter 155 Mbits/s Data Input  
88  
I
Supply  
Transmitter Digital Ground  
89  
I
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
SUPPLY Transmitter Digital Ground  
90  
I
91  
I
92  
I
93  
I
94  
I
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
95  
I
96  
I
97  
I
98  
I
Supply  
Transmitter Digital Ground  
99  
I
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
LVPECL Transmitter 155 Mbits/s Data Input  
SUPPLY Transmitter Digital Ground  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
I
I
I
I
I
LVPECL Transmitter 155 Mbits/s LSB Data Input  
LVPECL Transmitter 155 Mbits/s LSB Data Input  
I
I
Supply  
Transmitter Digital Ground  
O
I
LVPECL Transmitter Parallel Reference Clock Output  
LVPECL Transmitter Parallel Reference Clock Output  
PCLKN  
TxDGND  
TxAGND  
Tx3.3D  
I
Supply  
Supply  
Supply  
Supply  
Transmitter Digital Ground  
I
Transmitter Analog Ground  
Transmitter Digital 3.3 V Supply  
Transmitter Analog 3.3 V Supply  
Future Function (I2C Clock)  
I
Tx3.3A  
I
NC  
I
PHINIT  
TXDIS  
LVPECL Phase Initialization  
I
TTL  
Transmitter Disable  
Future Function (I2C Data)  
NC  
O
I
PHERR  
LLOOP  
LVPECL Phase Error  
LVTTL  
LVTTL  
Supply  
LVTTL  
Supply  
Supply  
Line Loopback (active-low)  
LOS  
O
I
Loss of Signal  
RxDGND  
OOF  
Receiver Digital Ground  
Out of Frame (enable frame detection)  
Receiver Digital Ground  
Receiver Digital 3.3 V Supply  
I
RxDGND  
Rx3.3D  
I
I
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).  
2. Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC, Ground,  
or any signal node.  
8
Agere Systems Inc.