Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Timing Characteristics (continued)
7
6
5
4
3
2
tPLH (TYP)
tPHL (TYP)
1
0
0
25
50
75
100 125
150
175 200
LOAD CAPACITANCE, CL (pF)
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 2. Typical Extrinsic Propagation Delay Versus Load Capacitance at 25 °C
2.4 V
INPUT
TRANSITION
1.5 V
0.4 V
tP1
tP2
VOH
VOL
OUTPUTS
OUTPUT
tPHH
tPLL
VOH
(VOH + VOL)/2
VOL
VOH
OUTPUT
OUTPUT
(VOH + VOL)/2
VOL
tPHL
tPLH
VOH
VOL
80%
20%
80%
20%
ttHL
ttLH
12-2677(F)
Figure 3. Driver Propagation Delay Timing
Agere Systems Inc.
7
AGERE [ AGERE SYSTEMS ]
