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AD7701ARS-REEL 参数 Datasheet PDF下载

AD7701ARS-REEL图片预览
型号: AD7701ARS-REEL
PDF下载: 下载PDF文件 查看货源
内容描述: [1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28, SSOP-28]
分类和应用: 光电二极管转换器
文件页数/大小: 21 页 / 346 K
品牌: AD [ ANALOG DEVICES ]
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INPUT SIGNAL CONDITIONING
Reference voltages from 1 V to 3 V may be used with the AD7701
with little degradation in performance. Input ranges that cannot
be accommodated by this range of reference voltages may be
achieved by input signal conditioning. This may take the form
of gain to accommodate a smaller signal range, or passive attenua-
tion to reduce a larger input voltage range.
Source Resistance
An RC filter may be added in front of the AD7701 to reduce
high frequency noise. With an external capacitor added from
A
IN
to AGND, the following equation will specify the maximum
allowable source resistance:
R
S
(Max)
=
f
CLKIN
62
100
mV
×
C
IN
/ (C
IN
×
(
C
IN
+
C
EXT
)
×
ln
V
E
+
C
EXT
)
If passive attenuators are used in front of the AD7701, care must
be taken to ensure that the source impedance is sufficiently low.
The AD7701 has an analog input with over 1 GΩ dc input
resistance. In parallel with this, there is a small dynamic load that
varies with the clock frequency (see Figure 13). Each time the
analog input is sampled, a 10 pF capacitor draws a charge packet
of maximum 1 pC (10 pF
×
100 mV) from the analog source
R1
A
IN
The practical limit to the maximum value of source resistance is
thermal (Johnson) noise. A practical resistor may be modeled as
an ideal (noiseless) resistor in series with a noise voltage source
or in parallel with a noise current source:
V
n
=
4
kTRf Volts
i
n
=
4
kTRf R Amperes
where
k
is Boltzmann’s constant (1.38
×
10
–23
J/K).
T
is temperature in degrees Kelvin (°C + 273).
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. Their open-
loop output resistance is normally only tens of ohms and, in any
case, most modern general-purpose op amps have sufficiently
fast closed-loop settling time for this not to be a problem. Offset
voltage in op amps can be eliminated in a system calibration
routine. With the wide dynamic range and small LSB size of the
reject most broadband noise above its cutoff frequency. How-
ever, in certain applications there may be a need for analog
input filtering.
Antialias Considerations
R2
C
EXT
C
IN
10pF
V
OS
100mV
AGND
Figure 13. Equivalent Input Circuit and Input Attenuator
with a frequency f
CLKIN
/256. For a 4.096 MHz CLKIN, this
yields an average current draw of 16 nA. After each sample, the
The equation that defines settling time is:
V
O
=
V
IN
1
e
t
[
RC
]
where
V
O
is the final settled value.
V
IN
is the value of the input signal.
R
is the value of the input source resistance.
C is the 10 pF sample capacitor.
t
is equal to 62/f
CLKIN
.
From this, the following equation can be developed, which
gives the maximum allowable source resistance,
R
S(MAX)
, for
an error of
V
E
:
The digital filter of the AD7701 does not provide any rejection
at integer multiples of the sampling frequency (nf
CLKlN
/256,
where n = 1, 2, 3 . . . ).
With a 4.096 MHz master clock, there are narrow (± 10 Hz)
bands at 16 kHz, 32 kHz, 48 kHz, and so on, where noise
passes unattenuated to the output.
However, due to the AD7701’s high oversampling ratio of 800
(16 kHz to 20 Hz), these bands occupy only a small fraction of
the spectrum and most broadband noise is filtered. The reduc-
tion in broadband noise is given by:
R
S
(MAX )
=
f
CLKIN
62
×(10
pF
)
×
l n
(100mV /V
E
)
e
OUT
=
e
IN
2
f
C
/
f
S
=
0.035
e
IN
where
e
lN
and
e
OUT
are rms noise terms referred to the input.
f
C
is the filter –3 dB corner frequency (f
CLKIN
/409600).
f
S
is the sampling frequency (f
CLKIN
/256).
Since the ratio of f
S
to f
CLKIN
is fixed, the digital filter reduces
broadband white noise by 96.5% independent of the master
clock frequency.
Provided the source resistance is less than this value, the analog
input will settle within the desired error band in the requisite 62
clock periods. Insufficient settling leads to offset errors. These
can be calibrated in system calibration schemes.
If a limit of 10
µV
(0.25 LSB at 16 bits) is set for the maximum
offset voltage, then the maximum allowable source resistance is
160 kΩ from the above equation, assuming that there is no
external stray capacitance.
REV. E
–11–