(V = +5 V, V = –5 V, AGND = DGND = 0 V, REF IN = +3 V, fCLK = 2.5 MHz
DD
SS
external. All specifications TMIN to TMAX unless otherwise noted.)
AD7874–SPECIFICATIONS
P aram eter
A Version B Version S Version Units
Test Conditions/Com m ents
SAMPLE-AND-HOLD
Acquisition T ime2 to 0.01%
Droop Rate2, 3
2
1
500
0
2
1
500
0
2
2
500
0
µs max
mV/ms max
kHz typ
ns min
–3 dB Small Signal Bandwidth3
Aperture Delay2
VIN = 500 mV p-p
40
200
4
40
200
4
40
200
4
ns max
ps typ
ns max
Aperture Jitter2, 3
Aperture Delay Matching2
SAMPLE-AND-HOLD AND ADC
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
T otal Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion
2nd Order T erms
70
–78
–78
71
–80
–80
70
–78
–78
dB min
dB max
dB max
fIN = 10 kHz Sine Wave, fSAMPLE = 29 kHz
fIN = 10 kHz Sine Wave, fSAMPLE = 29 kHz
fIN = 10 kHz Sine Wave, fSAMPLE = 29 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 29 kHz
–80
–80
–80
–80
–80
–80
–80
–80
–80
dB max
dB max
dB max
3rd Order T erms
Channel-to-Channel Isolation2
DC ACCURACY
Resolution
Relative Accuracy
12
±1
±1
±5
±5
5
12
±1/2
±1
±5
±5
5
12
±1
±1
±5
±5
5
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Differential Nonlinearity
Positive Full-Scale Error4
Negative Full-Scale Error4
Full-Scale Error Match
Bipolar Zero Error
No Missing Codes Guaranteed
Any Channel
Any Channel
Between Channels
Any Channel
Between Channels
±5
4
±5
4
±5
4
Bipolar Zero Error Match
ANALOG INPUT S
Input Voltage Range
Input Current
±10
±600
±10
±600
±10
±600
Volts
µA max
REFERENCE OUT PUT S
REF OUT
3
3
3
V nom
REF OUT Error @ +25°C
T MIN to T MAX
±0.33
±1
±0.33
±1
±0.33
±1
% max
% max
REF OUT T emperature Coefficient
Reference Load Change
±35
±1
±35
±1
±35
±2
ppm/°C typ
mV max
Reference Load Current Change (0–500 µA)
Reference Load Should Not Be Changed During Conversion
REFERENCE INPUT
Input Voltage Range
Input Current
2.85/3.15 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%
±1
±1
±1
µA max
Input Capacitance3
10
10
10
pF max
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
10
2.4
0.8
±10
10
2.4
0.8
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
V max
µA max
pF max
3
Input Capacitance, CIN
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
DB0–DB11
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
VDD = 5 V ± 5%; ISOURCE = 40 µA
VDD = 5 V ± 5%; ISINK = 1–6 mA
Floating-State Leakage Current
±10
±10
±10
µA max
VIN = 0 V to VDD
Floating-State Output Capacitance 10
Output Coding
10
10
pF max
2s COMPLEMENT
POWER REQUIREMENT S
VDD
VSS
+5
–5
+5
–5
+5
–5
V nom
V nom
±5% for Specified Performance
±5% for Specified Performance
IDD
ISS
18
12
150
18
12
150
18
12
150
mA max
mA max
mW max
CS = RD = CONVST = +5 V; T ypically 12 mA
CS = RD = CONVST = +5 V; T ypically 8 mA
CS = RD = CONVST = +5 V; T ypically 100 mW
Power Dissipation
NOT ES
1T emperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2See T erminology.
3Sample tested @ +25°C to ensure compliance.
4Measured with respect to the REF IN voltage and includes bipolar offset error.
5For capacitive loads greater than 50 pF a series resistor is required.
Specifications subject to change without notice.
–2–
REV. C
ADI [ ADI ]
