Table IA. Electrical performance characteristics.
Test
│ Symbol │
Conditions
│Group A │Device │ Limits
│ Unit
│
│
│
│
│
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VDD ≤ 5.5 V 1/
unless otherwise specified
│subgroups │ type
│
│
│
│
│
│
│
│
│
│
│
│
│ Min │ Max │
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Output low voltage
Output high voltage
│VOL
│
│test one output at a time,
│VDD = 4.5 V, IOL = 4.0 mA
│
│test one output at a time,
│VDD = 4.5 V, IOH = -3.2 mA
│
│
│
│
│
│ 1,2,3
│
│
│ 1,2,3
│
│
│ 1,2,3
│
│ 1,2,3
│
│All
│
│
│All
│
│
│All
│
│01-04
│
│05
│All
│
│
│
│All
│
│
│All
│
│
│01,02
│
│05
│
│
0.4 │ V
│
│
│
3.7 │
│
│
│ V
│
│VOH
│
│
│VIL
│
│VIH
│
│
│
│
│
│
Input low voltage
Input high voltage
0.8 │ V
│
2.0 │
│VDD+ │
2.2 │ 0.3
│ V
│
│
│
Standby supply current │IDD
│outputs unloaded,
│VDD = 5.5 V,
│VIN = VDD or GND
│
│VDD = 5.5 V,
│VIN = VDD or GND
│
│VDD = 5.5 V,
│VOUT = VDD or GND
│
│ 1,2,3
│
│
│
│ 1,2,3
│
│
│ 1,2,3
│
│
│
│
│
│
25 │ mA
│
│
│
│IIL
│
│
│
│
│
│ µA
│
│
│ µA
│
│
Input leakage current
-10 │10
│
│
Output leakage current │IOZ
-10 │ 10
│
│
│IOS
│
│
│
│
│
│CI/O
│
│
│
Output short circuit
current
│
│
│ 2/
│VOUT = VDD │ 1,2,3
│
│
20 │ 140 │ mA
│
│
│
│
│
│
│
│
0 │ 160
│
│
│
│VOUT = GND │ 1,2,3
│
│
│01,02 │ -100 │-10
│
│
│
│
│
│
│
│
│05
│All
│
│ -100 │ 0
I/O terminal
capacitance
│See 4.4.1c, f = 1.0 Mhz,
│VOUT = 0 V
│
4
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 20 │ pF
│
│
│
│
│
│
│
│
│
│
Functional tests
│FT 3/ │VDD = 4.5 V , See 4.4.1e and f │ 7,8A,8B │All
│
│
│
│
Binning circuit delay
│tPBLH,
│
│tPBHL
│
│
│
│
│
│
│
│See figure 3, VIL = 0 V,
│VIH = 3.0 V, VDD = 4.5 V,
│VOUT = 1.5 V
│ 9,10,11 │ 01
│ 186 │ ns
│
│ 158 │
│
│
│
│
│
│
│
│
│
│
│
│ 02
│
│
4/
│
│
│
│
│
│
│
│
│ 03
│168.2 │
│
│
│
│ 04
│
│142.9 │
│
│
│ 05
│
│168.2 │
│
│
1/ All tests shall be performed under the worst case condition unless otherwise specified. Devices supplied to this drawing
will meet levels M, D, P, L, R, and F, of irradiation. However, this device is only tested at the "F" level. Pre and post
irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical
measurements for any RHA level, TA = +25°C.
2/ VDD = 4.5 V for minimum limits and VDD = 5.5 V for maximum limits. Test one output at a time,
duration of short circuit condition shall not exceed one second. This test for devices 01, 02, and 05 only.
3/ Devices are functionally tested using a serial scan test method. Data is shifted into the SDI pin and the DCLK pin is
used as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete
functional test to be performed. The outputs of the module can be read by shifting out the output response or by
monitoring the PRA and PRB pins. These tests form a part of the manufacturer's test tape and shall be maintained by
the approved source(s) of supply and shall be made available upon request by the preparing or acquiring activity.
4/ Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning
circuit shall be programmed into all device prior to screening. The binning circuit consists of one input buffer plus 28
logic modules plus one output buffer. The logic modules are distributed along two sides of the device. These modules
are configured as inverting and non-inverting buffers and are connected through programmed antifuses with typical
capacitive loading.
SIZE
STANDARD
5962-90965
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
G
SHEET
6
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
