Core3DES
Core3DES Verification
I/O Signal Descriptions
The comprehensive verification simulation testbench
(included with the Netlist and RTL versions of the core)
verifies the Core3DES macro against test cases listed in
NIST Special Publication 800-20, Modes of Operation
Validation System for the Triple Data Encryption
Algorithm (TMOVS): Requirements and Procedures. The
testbench applies several tests to the Core3DES macro,
including: variable plaintext tests, variable cipher key
tests, permutation operation tests, substitution table
tests, and Monte Carlo tests. Using the supplied user
testbench as a guide, the user can easily customize the
verification of the core by adding or removing any of the
tests listed in NIST Special Publication 800-20 or by
adding any custom test cases.
The port signals for the Core3DES macro are defined in
Table 2 and illustrated in Figure 6. Core3DES has 202 I/O
signals that are described in Table 2. Most arrayed ports
are labeled with indices that begin with the number 1
(most significant bit) and ascend up to the width of the
arrayed port (least significant bit, which is 64 for most of
the arrayed ports in this core). The arrayed ports are
labeled in this fashion to correspond with the
nomenclature described in Federal Information
Processing Standards Publication 46-3 (FIPS PUB 46-3).
The only deviation from this nomenclature is the Key
Select output bus, which descends from 1 down to 0.
Table 2 • Core3DES I/O Signal Descriptions
Name
NRESET
CLK
Type
Input
Description
Active-low asynchronous reset
Input
System clock: reference clock for all internal Triple DES logic
EN
Input
Enable signal: set to '1' for normal continuous operation, set to '0' to pause
Synchronous clear signal: set to '1' to clear logic at any time
Encrypt/Decrypt: '1' to Encrypt, '0' to Decrypt
CLR
Input
ED
Input
PCHK
K[1:64]
D[1:64]
Q[1:64]
QVAL
KSEL[1:0]
Input
Parity Check: set to '1' to enable parity checking of cipher key bits
Key: 64 bit (56 bits + 8 parity bits) cipher key input bus (time-multiplexed K1,K2,K3 sub-keys)
Data in: 64 bit data input bus
Input
Input
Output
Output
Output
Data out: 64 bits of ciphertext (for Encrypt operation, plaintext for Decrypt operation)
Q Valid: '1' indicates that valid Encrypt/Decrypt data is available on Q [1:64]
Key Select: Selection bits for cipher key sub-keys K1, K2, and K3. When 00: K1 needs to be presented on
the K[1:64] input bus, when 01: K2 needs to be presented on the K[1:64] input bus, when 10: K3 needs to
be presented on the K[1:64] input bus
PERR
Output
Parity Error: '1' indicates that a parity error has occurred on the K cipher key input bits
NRESET
CLK
EN
Q[1:64]
CLR
Core3DES
ED
QVAL
KSEL[1:0]
PCHK
K[1:64]
D[1:64]
PERR
Figure 6 • Core3DES I/O Signal Diagram
v5.0
5
ACTEL [ Actel Corporation ]
