Ei16C550
FIFO UART
Semiconductor, Inc.
The UART includes a programmable baud generator
which is capable of dividing the timing reference clock
input by divisors of 1 to (216-1), and producing a 16 x
clock to drive the receiver logic. Also included in the
UART is a complete MODEM control capability, and
processor interrupt system that may be software tai-
lored to the users requirement to minimize the com-
puting needed to handle the communications link.
BLOCK DIAGRAM
RECEIVER
SHIFT
REGISTER
INTERNAL
DATA BUS
(10)
RECEIVER
BUFFER
REGISTER
SIN
DATA
BUS
BUFFER
(1-8)
D7-D0
LINE
CONTROL
REGISTER
RECEIVER
TIMING
&
(9)
RCLK
(28)
(27)
(26)
(12)
(13)
(14)
(25)
(35)
(22)
(21)
(19)
(18)
(23)
(24)
(16)
(17)
(29)
DIVISOR
LATCH
(LS)
A0
A1
A2
CS0
CS1
CS2•
ADR
MR
CONTROL
BAUD
GENERATOR
(15)
DIVISOR
LATCH
(MS
BAUDOUT
TRANSMITTER
TIMING
SELECT
LINE
STATUS
REGISTER
AND
CONTROL
LOGIC
DISTR
&
DISTR•
DOSTR
DOSTR•
DDIS
TXRDY•
XTAL1
CONTROL
FIFO
(11)
TRANSMITTER
SHIFT
REGISTER
SOUT
MODEM
CONTROL
REGISTER
XTAL2
RXRDY•
(32)
(36)
(33)
(37)
(38)
(39)
RTS•
CTS•
DTR•
DSR•
DCD•
MODEM
STATUS
REGISTER
MODEM
CONTROL
LOGIC
INTERRUPT
ENABLE
REGISTER
•
RI
INTERRUPT
CONTROL
LOGIC
(40)
(20)
(34)
(31)
POWER
SUPPLY
3.3, 5V
GND
OUT1•
OUT2•
INTERRUPT
ID
(30)
INTRPT
REGISTER
FIFO
CONTROL
REGISTER
8
A1PROS [ A1 PROS CO., LTD. ]
