Ai9943
Timing Specifications
( CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in the section “CCD-mode Timing”)
Value
Parameter
Symbol
Unit
Min
Typ
Max
Sample Clocks
tCONV
40
16
ns
DATACLK, SHP, SHD Clock Period
tADC
tSHP
tSHD
tCOB
tS1
20
10
10
20
10
20
3.0
ns
ns
DATACLK High / Low Pulse Width
SHP Pulse Width
ns
SHD Pulse Width
2
Pixels
ns
CLPOB Pulse Width (*1)
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
tS2
16
ns
tID
ns
Data Outputs
tOD
9.5
9
ns
Output Delay
Cycles
Pipeline Delay
Serial Interface
tSCLK
tLS
10
10
10
10
10
MHz
ns
Maximum SCK Frequency
SL to SCK Setup Time
tLH
ns
SCK to SL Hold Time
tDS
ns
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
tDH
ns
(*1): Minimum CLPOB pulse width is for functional operation only. Wider pulses are recommended to obtain
low noise clamp performance.
4
A1PROS [ A1 PROS CO., LTD. ]
