A-Data
ADD8608A8A
AC Characteristics
-75BA
-75B
Parameter
Symbol
tCK2.5
Unit
ns
Min
7.5
7.5
Max
12
Min
7.5
Max
12
System clock
Cycle time
/CAS Latency = 2.5
/CAS Latency = 2
tCK2
12
10
12
Clock high pulse width
tCHW
tCLW
tAC
0.45
0.45
-0.75
-0.75
0.75
65
0.55
0.45
0.45
0.55
CLK
CLK
ns
Clock low pulse width
0.55
0.55
Access time form CK to /CK
Data strobe edge to clock edge
0.75
-0.75
-0.75
0.75
65
0.75
tDQSCK
0.75
0.75
ns
Clock to first rising edge of DQS delay tDQSS
1.25
1.25
CLK
ns
/RAS cycle time
tRC
-
-
/RAS to /CAS delay
tRCD
tRAS
tRP
20
-
20
-
ns
/RAS active time
45
120K
45
120K
ns
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
20
-
20
-
ns
tRRD
tCCD
tDS
15
-
15
-
ns
1
-
1
-
CLK
ns
Data-in setup time (to DQS)
Data-in hold time (to DQS)
0.5
0.5
0.2
0.2
0.9
0.9
0.35
0.35
0
-
0.5
0.5
0.2
0.2
0.9
0.9
0.35
0.35
0
-
tDH
-
-
ns
DQS Falling Edge to CLK Setup Time tDSS
DQS Falling Edge Hold Time from CLK tDSH
-
-
CLK
CLK
ns
-
-
-
-
Input setup time
tIS
Input hold time
tIH
-
-
ns
DQS-in high level width
DQS-in low level width
tDSH
tDSL
-
-
CLK
CLK
ns
-
-
Clock to DQS write preamble setup time tWPRES
-
-
Write preamble
tWPST
tDQSQ
tMRD
0.4
06
0.5
0.4
06
0.5
CLK
ns
Data strobe edge to output data edge
Mode register set cycle time
DQS read preamble
15
15
tRPRE
0.9
1.1
0.9
1.1
CLK
Rev 2 April, 2002
7
ADATA [ ADATA Technology Co., Ltd. ]
